1. Field of the Invention
The present invention relates to a bipolar transistor design, and, in particular, to a process for forming a vertically isolated bipolar device that can be incorporated into a CMOS process flow with a minimum number of additional steps.
2. Discussion of the Related Art
FIG. 1 shows a cross-sectional view of a conventional vertical PNP bipolar transistor structure. Conventional PNP bipolar transistor structure 100 is formed in P-well 102. P-well 102 is created within P-type silicon substrate 104. The collector of bipolar transistor 100 is formed by P-well 102 and buried P+ layer 106. Buried P+ layer 106 is connected to collector contact 108 by P+ sinker structure 110. Collector contact 108 and P+ sinker 110 are electrically isolated from the base and emitter by intra-device isolation structure 112.
The base of bipolar transistor 100 is formed by N-type layer 114 having N+ base contact region 116. N+ base contact region 116 is self-aligned to oxide spacer 118 formed on sidewall 120a of extrinsic P+ polysilicon emitter 120. Polysilicon emitter contact component 120b of diffused polysilicon emitter structure 120 overlies P+ single crystal emitter component 120c. Polysilicon emitter contact component 120b of diffused polysilicon emitter 120 is separated from base 114 by dielectric layer 124.
Older IC designs tended to use only bipolar transistors of the same type, for example exclusively PNP or NPN. In such circuits, it was possible for the transistors to share a common collector biased at a constant value. However, the ever-increasing demand for faster processing speeds and enhanced flexibility has dictated that PNP and NPN bipolar transistors be utilized together in the same circuit, and that they be employed in conjunction with MOS transistors. As a result, it has become increasingly important to electrically isolate individual bipolar devices formed within the same silicon substrate.
One way of providing such isolation is through silicon-on-insulator (SOI) technology. FIG. 2 shows a vertical PNP bipolar transistor 200 formed in an SOI isolation scheme.
PNP bipolar transistor 200 is similar to bipolar transistor 100 of FIG. 1, except bipolar transistor 200 is laterally isolated from adjacent semiconducting devices by dielectric-filled trenches 202. PNP bipolar transistor 200 is vertically isolated from underlying P-type silicon 204 by buried oxide layer 206.
SOI isolated bipolar transistor 200 of FIG. 2 is suitable for a number of applications. However, this design suffers from the serious disadvantage of being relatively difficult and expensive to fabricate. Specifically, formation of buried oxide layer 206 within underlying P-type silicon 204 entails complex processing steps which substantially elevate cost.
One way of forming buried oxide layer 206 is high-energy ion implantation of oxygen into the underlying silicon, followed by oxidation. The expense of this step is attributable to the complex ion implantation equipment required, and the difficulty of ensuring complete oxidation deep within the silicon.
An alternative way of forming the buried oxide layer is to join oxide surfaces of two separate silicon wafers, and then remove backside silicon of one of the wafers to produce a surface suitable for epitaxial growth. The high cost of this process is associated with the difficulty in effectively bonding together the oxide surfaces to form an single integrated wafer structure that is substantially free of defects.
Many other methods exist for forming a buried oxide layer in addition to the those specifically described above. However, these processes are also fraught with the potential for error, resulting in increased defect densities and high production costs.
Therefore, it is desirable to utilize a process flow for forming a vertically isolated bipolar transistor device compatible with CMOS processes which minimizes both the number and cost of additional processing steps.